`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:32:11 11/27/2024
// Design Name:   TS_Gate
// Module Name:   C:/CYH/ISE/7/Lab7/Test02_TS_Gate.v
// Project Name:  Lab7
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: TS_Gate
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Test02_TS_Gate;

	// Inputs
	reg [7:0] A;
	reg EN_;

	// Outputs
	wire [7:0] F;

	// Instantiate the Unit Under Test (UUT)
	TS_Gate uut (
		.A(A), 
		.EN_(EN_), 
		.F(F)
	);

	initial begin
		// Initialize Inputs
		A = 0;
		EN_ = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#100 EN_=1; A=8'b0000_0001;
		#100 EN_=1; A=8'b0000_1000;
		
		#100 EN_=0; A=8'b0000_0001;
		#100 EN_=0; A=8'b0000_0010;
		#100 EN_=0; A=8'b0000_0100;
		#100 EN_=0; A=8'b0000_1000;
		
	end
      
endmodule

